In most modern telecommunication networks, a community of subscribers are connected to a central office switch through a two-way distributed network, which may include one or more transmission facilities, e.g., microwave, optical, electrical, etc., and which may utilize both digital and analog transmission protocols. In particular, between the central office switch and a respective subscriber termination, e.g., a remotely located subscriber line card, telecommunication signals are commonly digitized and multiplexed for transport over relatively high bandwidth shared transmission facilities, e.g., optical fiber, for greater network efficiency.
By way of example, in an exemplary optical communication network, an optical line terminal ("OLT") located at a central office transmits digital telecommunications data signals--i.e., pulse-code-modulated ("PCM") voice or data--between a co-located switch and a number of remotely located optical network units ("ONUs"), wherein the data is transmitted optically between the OLT and the respective ONUs over optical fibers, and electrically between the OLT and the switch. More particularly, the OLT terminates respective "bus side," or "switch side," communication lines (e.g., E1 or T1 lines) on one end and "fiber side" optical fibers on another. In the downstream direction, the OLT cross-connects PCM data contained in byte-size time-division-multiplexed bus side channels into designated fiber side channels, which are then packetized and converted from electrical to optical signals for transmission to respective ONUs. Similarly, in the upstream direction, the OLT converts receives optical signals to electrical signals, disassembling the incoming data packets into fiber side channels, which are then cross-connected into respective assigned switch channels for transmission to the switch.
Cross-connecting the respective switch and fiber channels is conventionally performed with a timeslot interchange switch circuit, wherein up to several thousand channels may be cross-connected in a single interchange system. For example, in a known cross-connect system, byte-size time-division-multiplexed switch channels transported on an eight-bit wide bus are input/output on one side of a timeslot interchange cross-connect system, and byte-size time-division-multiplexed fiber channels transported in serial bit streams are output/input at the other side, wherein the transmission of data channels on both sides of the cross-connect system is repeated at a data frame rate of eight KHz, i.e., with eight bits/channel transmitted every 125 microseconds in each direction, for an overall data rate of 64,000 bits per second (i.e., 64 kbps), per channel.
To perform the cross-connection of the respective PCM data channels, the timeslot interchange circuit must temporarily store the respective bytes of data for each channel in a unique location in an associated cross-connect memory, which is duplicated in both the upstream and downstream directions. For example, in the downstream direction, this has been done by addressing a left port of a dual-port memory with a timeslot counter for the switch channel side, and by addressing a right port of the same dual-port memory with the data from a control store memory containing the bus side channel number to be cross-connected to each fiber timeslot for the fiber channel side. The data buses of the control store memory are connected directly to byte-wide registers that receive and transmit data on the bus side from and to a byte-wide bus, and on the fiber side to parallel/serial and serial/parallel converters connected to opto-electrical circuitry, respectively. The control store memory is addressed by a fiber side timeslot counter. Data for each channel is stored in the cross-connect memory at an address corresponding to its bus side timeslot number. The control store memory is programmed through a second port by a microprocessor, with each address containing the bus side timeslot number of the channel to be cross-connected to the fiber timeslot having the same number as the address.
Higher capacity interfaces, such as Integrated Services Digital Network (ISDN) channels, can be carried over multiple 64 kbps channels internal to the network. To maintain the byte sequencing of these higher rate interfaces, timeslot interchange memories are usually organized into two banks that are alternately read from, and written to, respectively, by the switch and fiber sides of each frame. Thus, for a first frame in the downstream direction, the bus side writes to bank "zero," while the fiber side reads from bank "one." In the next frame, the bus side writes to bank one while the fiber side reads the data in bank zero, i.e., that was just written by the bus side, albeit in a different order. In this manner, all the data contained in a single frame on the bus side is carried in the next frame on the fiber side, and byte sequencing is maintained when multiple internal channels are reassembled into a higher rate interface to a respective ONU.
The cross-connection of signalling information associated with individual switch and fiber PCM data channels is complicated by the variations in multiframe signalling protocol used throughout the world. For example, under the applicable international (i.e., "E1") telecommunication transmission standard, signalling information is carried over a "signalling multiframe" comprising sixteen data frames, wherein each E1 data frame comprises thirty-two byte-size data channels transmitted at the basic telephony rate of 8 KHz (i.e., every 125 usecs), for an overall data rate of 2.048 mega bits per second (mbps). In particular, each E1 data frame contains a framing channel followed by fifteen subscriber PCM channels, a signalling channel, and another fifteen subscriber PCM channels, respectively, wherein each signalling channel carries four bits of signalling information each for two of the respective subscriber PCM channels (i.e., with the first signalling channel of each multiframe unused), such that, over the course of a sixteen frame signalling multiframe, each of the thirty PCM data channels has four signalling bits transmitted to go with sixteen bytes of PCM data.
On the other hand, under the applicable U.S. (i.e., "T1") standard, signalling multiframes comprising twenty-four T1 data frames are used, wherein each T1 data frame comprises twenty-four byte-size subscriber PCM channels transmitted, along with a single framing bit, every 125 usecs for an overall data rate of 1.544 mbps. Unlike the E1 standard, a "bit robbing" methodology is employed to carry signalling information in a T1 frame. In particular, each subscriber PCM channel carries one bit of its own signalling information in its least significant bit location every sixth frame. In this manner, over the course of a T1 signalling multiframe, each of the twenty-four subscriber PCM channels has four signalling bits transmitted to go with the twenty-four bytes of PCM data.
More recently, some signalling cross-connect systems have expanded on the above-described timeslot interchange circuit, by enlarging the cross-connect control store memory to contain sixteen locations for use in communication systems operating under the E1 standard (or twenty-four locations for communication systems operating under the T1 standard) for each fiber side timeslot, so that different fiber and switch timeslots can be cross-connected in each frame of a signalling multiframe. This configuration allows for signalling information for each of the fifteen (or twenty-four) subscriber channels associated with each bus side signalling channel to be cross-connected to the signalling information location associated with any of the fifteen (or twenty-four) subscriber channels in any of the fiber side signalling channels.
However, to ensure that the signalling information is not overwritten by another channel before it is "read out" by the respective other side of the cross-connect circuit, the signalling information associated with each subscriber channel must be stored at a unique address, which requires that the cross-connect memories be fifteen times (for E1) or twenty-four times (for T1) as large as the memory of a "simple" timeslot interchange circuit described above. In addition, the control store memory must also have fifteen (or twenty-four) times as many addresses with five more bits per location, since five is the first integer greater than the base-two logarithm of twenty-four. The larger control store also requires more complex firmware to write to fifteen (or twenty-four) locations for each subscriber channel and other locations for the associated signalling channels.
In addition to cross-connection of subscriber channels, the OLT must also perform the assembly and disassembly of data packets transmitted to, and received from, the respective ONUs. Conventionally, this packet assembly/disassembly ("PAD") function is performed by a "packet engine" that is separate from the cross-connect circuitry, wherein large memory buffers are required to accommodate the different data transmission rates on the respective switch and fiber sides of the OLT. A further control store is also needed to be able to control the PAD function for each fiber timeslot, e.g., wherein each further control store location contains a word that specifies whether the particular timeslot contains an overhead data pattern (e.g., for clock recovery or optical level acquisition), an OLT/ONU communications channel, or a subscriber PCM data channel from the bus side backplane bus.
Thus, there is a need for a system that combines cross-connect and packet engine circuitry, stores signalling information efficiently, and significantly reduces both the complexity and the memory requirements of the respective system hardware and firmware over the known art.